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Number of items: 8.
Wang, Lun Yao, Xia, Y, Yang, M and Almaini, A E A (2006) An approach to obtain compact multi-level mixed polarity Reed-Muller functions with onset table. WSEAS Transactions on Circuits and Systems, 5 (5). pp. 625-632. ISSN 11092734
Xia, Y, Ye, X, Wang, Lun Yao, Tao, J and Almaini, A E A (2005) A novel low power FSM partition approach and its implementation. 23rd NORCHIP Conference 2005. pp. 102-105. ISSN 1 4244 0064 3
Xia, Y, Ye, X, Wang, Lun Yao, Zou, Z and Almaini, A E A (2005) Novel synthesis method of mixed polarity reed-muller functions. In: Third IASTED International Conference on Circuits, Signals and Systems, CSS 2005, 24 October 2005 - 26 October 2005, California, Marina del Rey.
Xia, Y, Wang, Lun Yao and Almaini, A E A (2005) A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20 (2). pp. 237-242. ISSN 1000 9000
Xia, Y, Ali, Belgasem and Almaini, A E A (2003) Area and power optimization of FPRM function based circuits. In: Proceedings of the 2003 IEEE INternational Symposium on Circuits and Systems. IEEE International Symposia on Circuits and Systems, 5 . IEEE, Circuits and Systems Society, Thailand, Bangkok, Mahanakorn University, V329-V332. ISBN 02714310
Xia, Y, Wu, X and Almaini, A E A (2003) Power minimization of FRPM functions based on polarity conversion. Journal of Computer Science and Technology, 18 (3). pp. 325-331. ISSN 1000 9000
Xia, Y and Almaini, A E A (2002) Genetic algorithm based state assignment for power and area optimisation. IEE Proceedings - Computers and digital techniques, 149 (4). pp. 128-133. ISSN 1350 2387
Xia, Y and Almaini, A E A (2002) Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38 (1). pp. 9-11. ISSN 0013 5194