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Number of items: 15.

Article

Yang, M, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2008) Techniques for dual forms of Reed-Muller expansion conversion. Integration, the VSLI Journal, 41 (1). pp. 113-122. ISSN 01679260

Yang, M, Xu, H, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2007) Exact minimization of large fixed polarity dual form of reed-muller functions. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology. pp. 1931-1933. ISSN 1424401611

Yang, M, Wang, Lun Yao and Almaini, A E A (2006) Fast conversion for large Canonical OR-coincidence functions. APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. pp. 1643-1646. ISSN 1424403871

Wang, Lun Yao, Xia, Y, Yang, M and Almaini, A E A (2006) An approach to obtain compact multi-level mixed polarity Reed-Muller functions with onset table. WSEAS Transactions on Circuits and Systems, 5 (5). pp. 625-632. ISSN 11092734

Xia, Y, Ye, X, Wang, Lun Yao, Tao, J and Almaini, A E A (2005) A novel low power FSM partition approach and its implementation. 23rd NORCHIP Conference 2005. pp. 102-105. ISSN 1 4244 0064 3

Yang, M, Almaini, A E A, Wang, Lun Yao and Wang, P (2005) FPGA placement using genetic algorithm with simulated annealing. ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005, 2. pp. 808-811. ISSN 0 7803 9210 8

Xia, Y, Wang, Lun Yao and Almaini, A E A (2005) A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20 (2). pp. 237-242. ISSN 1000 9000

Wang, Lun Yao and Almaini, A E A (2003) Multilevel logic simplification based on containment recursive paradigm. IEE Proceedings - Computers and digital techniques, 150 (4). pp. 218-226. ISSN 1350 2387

Almaini, A E A and Wang, Lun Yao (2002) Exact minimisation of large multiple output FPRM functions. IEE Proceedings - Computers and digital techniques, 149 (5). pp. 203-212. ISSN 1350 2387

Wang, Lun Yao and Almaini, A E A (2002) Optimisation of Reed-Muller PLA implementations. IEE Proceedings - Circuits Devices and Systems, 149 (2). pp. 119-128. ISSN 1350-2409

Wang, Lun Yao, Chen, X and Almaini, A E A (1998) Modulo correlativity and its application in a multiple valued logic system. International Journal of Electronics, 85 (5). pp. 561-570. ISSN 0020 7217

Wang, Lun Yao, Chen, X and Almaini, A E A (1998) Algebraic properties of multiple-valued modulo systems and their applications to current-mode CMOS circuits. IEE Proceedings - Computers and digital techniques, 145 (5). pp. 364-368. ISSN 1350 2387

Book Section

Xu, H, Yang, M, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2007) An efficient transformation method for DFRM expansions. In: 7th International Conference on ASIC, 2007. ASICON '07. IEEE, Computer Society, pp. 1158-1161. ISBN 978-1-4244-1132-0

Yang, M, Almaini, A E A, Wang, Lun Yao and Wang, P (2005) An evolutionary approach for symmetrical field programmable gate array placement. In: Research in Microelectronics and Electronics, 2005 PhD. Conference Proceedings, 1 . IEEE, pp. 169-172. ISBN 0-7803-9345-7

Conference or Workshop Item

Xia, Y, Ye, X, Wang, Lun Yao, Zou, Z and Almaini, A E A (2005) Novel synthesis method of mixed polarity reed-muller functions. In: Third IASTED International Conference on Circuits, Signals and Systems, CSS 2005, 24 October 2005 - 26 October 2005, California, Marina del Rey.

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