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Number of items: 39.

Al-Jassani, ban Adil, Urquhart, Neil B and Almaini, A E A (2011) State assignment for sequential circuits using multi-objective genetic algorithm. IET Computers & Digital Techniques, 5 (4). pp. 296-305. ISSN 1751-8601

Al-Jassani, ban Adil, Urquhart, Neil B and Almaini, A E A (2010) Manipulation and optimization techniques for Boolean logic. IET proceedings on computer and digital techniques , 4 (3). pp. 227-239.

Al-Jassani, ban Adil, Urquhart, Neil B and Almaini, A E A (2009) Minimization of incompletely specified mixed polarity Reed Muller functions using genetic algorithm. In: 3rd IEEE international conference on Signal Circuits and Systems, 2009 November, Tunis.

Xu, H, Yang, M and Almaini, A E A (2008) Efficient bidirectional conversion between RM and DFRM expansions. Mediterranean Journal of Electronics & Communications, 4 (3). pp. 84-89. ISSN 1744-2400

Yang, M, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2008) Techniques for dual forms of Reed-Muller expansion conversion. Integration, the VSLI Journal, 41 (1). pp. 113-122. ISSN 01679260

Al-Jassani, ban Adil, Urquhart, Neil B and Almaini, A E A (2008) Optimization of MPRM functions using tabular techniques and genetic algorithms. The Mediterranean Journal of Electronics and Communications, 4 (4). pp. 115-125. ISSN 1744-2400

Xu, H, Yang, M, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2007) An efficient transformation method for DFRM expansions. In: 7th International Conference on ASIC, 2007. ASICON '07. IEEE, Computer Society, pp. 1158-1161. ISBN 978-1-4244-1132-0

Wei, Bin, Sharif, MY, Binnie, David and Almaini, A E A (2007) Adaptive PN code acquisition in multi-path spread spectrum communications using FPGA. In: IEEE 13th International Symposium on Signals, Circuits and Systems, ISSCS 2007, July 2007, Lasi, Romania.

Oh, P and Almaini, A E A (2007) Decision diagrams using 2 variable nodes. WSEAS Transactions on Circuits and Systems, 6 (3). pp. 372-379. ISSN 11092734

Faraj, Khalid and Almaini, A E A (2007) Optimal expression for fixed polarity dual Reed-Muller forms. WSEAS Transactions on Circuits and Systems, 6 (3). pp. 364-371. ISSN 11092734

Faraj, Khalid and Almaini, A E A (2007) Minimization of dual Reed-Muller forms using dual property. WSEAS Transactions on Circuits and Systems, 6 (1). pp. 9-15. ISSN 1109 2734

Yang, M, Xu, H, Wang, Lun Yao, Tong, Jiarong R and Almaini, A E A (2007) Exact minimization of large fixed polarity dual form of reed-muller functions. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology. pp. 1931-1933. ISSN 1424401611

Yang, M, Wang, Lun Yao and Almaini, A E A (2006) Fast conversion for large Canonical OR-coincidence functions. APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. pp. 1643-1646. ISSN 1424403871

Wie, Bin, Sharif, MY, Almaini, A E A and Binnie, David (2006) PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA. In: Proceedings of IEEE 13th International Conference on Systems, Signals & Image Processing, IWSSIP’06,, 21-23 September 2006, Budapest.

Wang, Lun Yao, Xia, Y, Yang, M and Almaini, A E A (2006) An approach to obtain compact multi-level mixed polarity Reed-Muller functions with onset table. WSEAS Transactions on Circuits and Systems, 5 (5). pp. 625-632. ISSN 11092734

Yang, M, Wang, P, Chen, X and Almaini, A E A (2005) Fast tabular based conversion methods for Canonical OR-Coincidence. In: EUROCON 2005 - The International Conference on Computer as a Tool. EUROCON, 1 . IEEE, Piscataway, New Jersey, USA, pp. 507-510. ISBN 9781424400492

Xia, Y, Ye, X, Wang, Lun Yao, Tao, J and Almaini, A E A (2005) A novel low power FSM partition approach and its implementation. 23rd NORCHIP Conference 2005. pp. 102-105. ISSN 1 4244 0064 3

Yang, M, Almaini, A E A, Wang, Lun Yao and Wang, P (2005) FPGA placement using genetic algorithm with simulated annealing. ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005, 2. pp. 808-811. ISSN 0 7803 9210 8

Wang, P, Liu, Y, Yang, M and Almaini, A E A (2005) Five-valued circuit quantitative theory and design of five-valued twisted-ring. In: ASICON 2005: Proceedings of the 6th International Conference on ASIC, 2005. IEEE Operations Center, Piscataway, NJ, pp. 354-357. ISBN 0780392108 & 9780780392106

Xia, Y, Ye, X, Wang, Lun Yao, Zou, Z and Almaini, A E A (2005) Novel synthesis method of mixed polarity reed-muller functions. In: Third IASTED International Conference on Circuits, Signals and Systems, CSS 2005, 24 October 2005 - 26 October 2005, California, Marina del Rey.

Xia, Y, Wang, Lun Yao and Almaini, A E A (2005) A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20 (2). pp. 237-242. ISSN 1000 9000

Yang, M, Almaini, A E A, Wang, Lun Yao and Wang, P (2005) An evolutionary approach for symmetrical field programmable gate array placement. In: Research in Microelectronics and Electronics, 2005 PhD. Conference Proceedings, 1 . IEEE, pp. 169-172. ISBN 0-7803-9345-7

Ali, Belgasem, Almaini, A E A and Kalganova, Tatiana (2004) Evolutionary algorithms and their use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines, 5 (1). pp. 11-29. ISSN 1389-2576

Cheng, J, Chen, X, Faraj, Khalid and Almaini, A E A (2003) Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. IEE Proceedings - Computers and digital techniques, 150 (6). pp. 397-402. ISSN 1350 2387

Wang, Lun Yao and Almaini, A E A (2003) Multilevel logic simplification based on containment recursive paradigm. IEE Proceedings - Computers and digital techniques, 150 (4). pp. 218-226. ISSN 1350 2387

Xia, Y, Ali, Belgasem and Almaini, A E A (2003) Area and power optimization of FPRM function based circuits. In: Proceedings of the 2003 IEEE INternational Symposium on Circuits and Systems. IEEE International Symposia on Circuits and Systems, 5 . IEEE, Circuits and Systems Society, Thailand, Bangkok, Mahanakorn University, V329-V332. ISBN 0-7803-7761-3

Xia, Y, Wu, X and Almaini, A E A (2003) Power minimization of FRPM functions based on polarity conversion. Journal of Computer Science and Technology, 18 (3). pp. 325-331. ISSN 1000 9000

Almaini, A E A and Wang, Lun Yao (2002) Exact minimisation of large multiple output FPRM functions. IEE Proceedings - Computers and digital techniques, 149 (5). pp. 203-212. ISSN 1350 2387

Xia, Y and Almaini, A E A (2002) Genetic algorithm based state assignment for power and area optimisation. IEE Proceedings - Computers and digital techniques, 149 (4). pp. 128-133. ISSN 1350 2387

Wang, Lun Yao and Almaini, A E A (2002) Optimisation of Reed-Muller PLA implementations. IEE Proceedings - Circuits Devices and Systems, 149 (2). pp. 119-128. ISSN 1350-2409

Xia, Y and Almaini, A E A (2002) Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38 (1). pp. 9-11. ISSN 0013 5194

Wang, Lun Yao, Chen, X and Almaini, A E A (1998) Modulo correlativity and its application in a multiple valued logic system. International Journal of Electronics, 85 (5). pp. 561-570. ISSN 0020 7217

Wang, Lun Yao, Chen, X and Almaini, A E A (1998) Algebraic properties of multiple-valued modulo systems and their applications to current-mode CMOS circuits. IEE Proceedings - Computers and digital techniques, 145 (5). pp. 364-368. ISSN 1350 2387

Bystrov, A and Almaini, A E A (1998) Reversed ROBDD circuits. Electronics Letters, 34 (15). pp. 1447-1449. ISSN 0013 5194

Almaini, A E A (1997) Semicustom IC for generating optimum generalised Reed-Muller expansions. Microelectronics Journal, 28 (2). pp. 129-142. ISSN 0026 2692

Almaini, A E A and Burnside, K (1996) Generalised Reed-Muller ASIC converter. In: 2nd International Conference on ASIC. IEEE & Shanghai Scientific and Technical Literature, pp. 73-76. ISBN 7-5439-0940-5

Guan, Zhicheng and Almaini, A E A (1995) One-bit adder design based on Reed-Muller expansions. International Journal of Electronics, 79 (5). pp. 519-529. ISSN 0020 7217

Almaini, A E A and Zhuang, N (1995) Using genetic algorithms for the variable ordering of Reed-Muller binary decision diagrams. Microelectronics Journal, 26 (5). pp. 471-480. ISSN 0026 2692

Guan, Zhicheng, Thomson, P and Almaini, A E A (1994) Parallel CMOS 2's complement multiplier based on 5:3 counter. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings.. IEEE, pp. 298-301. ISBN 0-8186-6565-3

This list was generated on Sun Aug 31 11:33:12 2014 IST.

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