PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA.

Research Output

In this paper the performance of a Cell Averaging Constant False Alarm Rate (CA-CFAR) Pseudo-Noise (PN) code adaptive detector is analysed for a single path communication channel. The detection process uses a digital Matched Filter (MF) and is implemented using Field Programmable Gate Array (FPGA) technology. The performance of the CA-CFAR detector is compared with Order Statistics CFAR (OS-CFAR), OR CFAR (OR-CFAR) and AND CFAR (AND-CFAR) detectors in terms of speed of acquisition and hardware requirement. Simulation results using Xilinx devices are presented confirming that the CA-CFAR adaptive PN code detector has a rapid acquisition speed (second best after AND-CFAR) and has the least implementation complexity compared to other three detectors.

Date:

21 September 2006
Publication Status:

Published

http://researchrepository.napier.ac.uk/output/244090 <p>Wie, B., Sharif, M., Almaini, A. E. A. & Binnie, D. (2006). PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA. In <i>Proceedings of IEEE 13th International Conference on Systems, Signals & Image Processing, IWSSIP’06</i></p>

Citation

Wie, B., Sharif, M., Almaini, A. E. A. & Binnie, D. (2006). PN code acquisition with a CA-CFAR adaptive digital matched filter and its realisation using FPGA. In Proceedings of IEEE 13th International Conference on Systems, Signals & Image Processing, IWSSIP’06