Automated synthesis and optimization of multilevel logic circuits.
Citation
Wang, L. Automated synthesis and optimization of multilevel logic circuits. (Thesis). Edinburgh Napier University. Retrieved from http://researchrepository.napier.ac.uk/id/eprint/4342
Authors
Keywords
Very Large Scaled Integrated (VLSI) circuits; symbolic logic; multilevel logic synthesis; Reed-Muller; polarity;
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