Edinburgh Napier University

  In this letter, a novel on-chip array antenna with high-performances is investigated which is based on CMOS 20μm Silicon technology for operation over 0.6-0.65 THz. The proposed array structure is constructed on three layers composed of Silicon-Ground-Silicon layers. The ground-plane has sandwiched between two silicon layers. Two antennas are implemented on the top layer, where each antenna is constituted from three sub-antennas. The sub-antennas are constructed from interconnected dual-rings. Also, the sub-antennas are interconnected to each other. This approach enlarges the effective aperture area of the array, which has caused to improve its performance parameters. Surface waves and substrate losses in the structure are suppressed with the metallic via-holes that have inserted through the three layers and implemented between the radiation elements. To excite the structure, a novel feeding mechanism is used comprising open-circuited microstrip lines located on the back side of the structure, which couple the electromagnetic energy from the bottom layer to the antennas on the top-layer through metasurface slot-lines in the middle ground-plane layer. The results show the proposed on-chip antenna array has an average radiation gain, efficiency, and isolation of 7.62 dBi, 32.67%, and -30 dB, respectively.