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A study of arithmetic circuits and the effect of utilising Reed-Muller techniques.

Guan, Zhigang (1995) A study of arithmetic circuits and the effect of utilising Reed-Muller techniques. PhD thesis, Edinburgh Napier University.

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    Abstract/Description

    Reed-Muller algebraic techniques, as an alternative means in logic design, became
    more attractive recently, because of their compact representations of logic functions
    and yielding of easily testable circuits. It is claimed by some researchers that ReedMuller
    algebraic techniques are particularly suitable for arithmetic circuits. In fact, no
    practical application in this field can be found in the open literature.
    This project investigates existing Reed-Muller algebraic techniques and explores their
    application in arithmetic circuits. The work described in this thesis is concerned with
    practical applications in arithmetic circuits, especially for minimizing logic circuits at
    the transistor level. These results are compared with those obtained using the
    conventional Boolean algebraic techniques. This work is also related to wider fields,
    from logic level design to layout level design in CMOS circuits, the current leading
    technology in VLSI. The emphasis is put on circuit level (transistor level) design. The
    results show that, although Boolean logic is believed to be a more general tool in logic
    design, it is not the best tool in all situations. Reed-Muller logic can generate good
    results which can't be easily obtained by using Boolean logic.
    F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being
    restricted to using a small gate set. This usually leads to generating more complex
    circuits. When a cell fault model, which is more suitable for regular and iterative
    circuits, such as arithmetic circuits, is used instead of the gate fault model in ReedMuller
    logic, a wider gate set can be employed to realize Reed-Muller functions. As a
    result, many circuits designed using Reed-Muller logic can be comparable to that
    designed using Boolean logic. This conclusion is demonstrated by testing many
    randomly generated functions.
    The main aim of this project is to develop arithmetic circuits for practical application.
    A number of practical arithmetic circuits are reported. The first one is a carry chain
    adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain
    is constructed to perform the carry operation. The proposed carry chain adder can be
    reconstructed to form a fast carry skip adder, and it is also found to be a good
    application for residue number adders. An algorithm for an on-line adder and its
    implementation are also developed. Another circuit is a parallel multiplier based on
    5:3 counter. The simulations show that the proposed circuits are better than many
    previous designs, in terms of the number of transistors and speed. In addition, a 4:2
    compressor for a carry free adder is investigated. It is shown that the two main
    schemes to construct the 4:2 compressor have a unified structure. A variant of the
    Baugh and Wooley algorithm is also studied and generalized in this work.

    Item Type: Thesis (PhD)
    Uncontrolled Keywords: Reed-Muller; logic design; arithmetic circuits; logic circuits; CMOS; carry chain;
    University Divisions/Research Centres: Faculty of Engineering, Computing and Creative Industries > School of Engineering and the Built Environment
    Dewey Decimal Subjects: 600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering
    Library of Congress Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
    Item ID: 4340
    Depositing User: Mrs Lyn Gibson
    Date Deposited: 15 Apr 2011 14:43
    Last Modified: 15 Apr 2011 14:43
    URI: http://researchrepository.napier.ac.uk/id/eprint/4340

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