Guan, Zhicheng, Thomson, P and Almaini, A E A (1994) Parallel CMOS 2's complement multiplier based on 5:3 counter. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings.. IEEE, pp. 298-301. ISBN 0-8186-6565-3Full text not available from this repository. (Request a copy)
A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.
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