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Parallel CMOS 2's complement multiplier based on 5:3 counter.

Guan, Zhicheng, Thomson, P and Almaini, A E A (1994) Parallel CMOS 2's complement multiplier based on 5:3 counter. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings.. IEEE, pp. 298-301. ISBN 0-8186-6565-3

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Abstract/Description

A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.

Item Type: Book Section
Print ISSN: 0818665653
ISBN: 0-8186-6565-3
Uncontrolled Keywords: Integrated circuits; CMOS; Computing; Parallel processing; Tree structures; VLSI circuits;
University Divisions/Research Centres: Faculty of Engineering, Computing and Creative Industries > School of Engineering and the Built Environment
Dewey Decimal Subjects: 000 Computer science, information & general works > 000 Computer science, knowledge & systems > 004 Data processing & computer science > 004.2 Systems analysis, design & performance
600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering > 621.38 Electronics & Communications engineering > 621.381 Electronics
Library of Congress Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Item ID: 2624
Depositing User: Dr. David A. Cumming
Date Deposited: 01 Jun 2009 12:32
Last Modified: 10 Oct 2013 15:12
URI: http://researchrepository.napier.ac.uk/id/eprint/2624

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