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One-bit adder design based on Reed-Muller expansions.

Guan, Zhicheng and Almaini, A E A (1995) One-bit adder design based on Reed-Muller expansions. International Journal of Electronics, 79 (5). pp. 519-529. ISSN 0020 7217

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Abstract/Description

It has been claimed for some time that the Reed-Muller technique can yield a simpler arithmetic circuit if it is employed in the design procedure. In fact, no practical application in this field can be found in the open literature. This paper attempts to demonstrate a practical one-bit adder design that is based on the Reed-Muller expansion. Although the one-bit adder is simple, no method can always guarantee to obtain both a time and area optimal circuit. In this paper, a procedure to design both a time and area optimal one-bit adder in static CMOS circuits is presented. Some issues are also addressed for practical logic circuit design.

Item Type: Article
Print ISSN: 0020 7217
Electronic ISSN: 1362-3060
Uncontrolled Keywords: Arithmetic circuits; Circuit design; CMOS; Logic circuits; Reed-Muller; One-bit adder; Time optimal; Area optimal;
University Divisions/Research Centres: Faculty of Engineering, Computing and Creative Industries > School of Engineering and the Built Environment
Dewey Decimal Subjects: 600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering > 621.38 Electronics & Communications engineering > 621.389 Computer engineering
Library of Congress Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Item ID: 2623
Depositing User: Dr. David A. Cumming
Date Deposited: 01 Jun 2009 12:03
Last Modified: 10 Oct 2013 13:36
URI: http://researchrepository.napier.ac.uk/id/eprint/2623

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