Xia, Y and Almaini, A E A (2002) Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38 (1). pp. 9-11. ISSN 0013 5194Full text not available from this repository. (Request a copy)
A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal <0.65. Power reduction can be as high as 86% when the input is idle.
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