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Differential CMOS edge-triggered flip-flop with clock gating.

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Xia, Y and Almaini, A E A (2002) Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters, 38 (1). pp. 9-11. ISSN 00135194

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Abstract/Description

A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal <0.65. Power reduction can be as high as 86% when the input is idle.

Item Type: Article
Print ISSN: 00135194
Uncontrolled Keywords: CMOS integrated circuits; Flip-flops; Edge-trigger; PSPICE simulation; Power saving;
University Divisions/Research Centres: Faculty of Engineering, Computing and Creative Industries > School of Engineering and the Built Environment
Dewey Decimal Subjects: 600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering > 621.38 Electronics & Communications engineering > 621.389 Computer engineering
600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering > 621.38 Electronics & Communications engineering > 621.381 Electronics
Library of Congress Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Item ID: 2594
Depositing User: Dr. David A. Cumming
Date Deposited: 14 May 2009 12:31
Last Modified: 05 Jul 2010 16:53
URI: http://researchrepository.napier.ac.uk/id/eprint/2594

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