A novel multiple-valued CMOS flip-flop employing multiple-valued clock.

Xia, Yinshui, Wang, Lun Yao and Almaini, A E A (2005) A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology, 20 (2). pp. 237-242. ISSN 1000 9000

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A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterised by improved storage capacity, flexible logic structure and reduced power dissipation.

Item Type: Article
Print ISSN: 1000 9000
Uncontrolled Keywords: Integrated circuits; CMOS; Flip-flop circuits; Multiple-valued clock; Computer systems; Computer logic; Performance evaluation;
University Divisions/Research Centres: Faculty of Engineering, Computing and Creative Industries > School of Engineering and the Built Environment
Dewey Decimal Subjects: 600 Technology > 620 Engineering > 621 Electronic & mechanical engineering > 621.3 Electrical & electronic engineering > 621.38 Electronics & Communications engineering > 621.389 Computer engineering
000 Computer science, information & general works > 000 Computer science, knowledge & systems > 004 Data processing & computer science > 004.2 Systems analysis, design & performance
Library of Congress Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Item ID: 2567
Depositing User: Users 10 not found.
Date Deposited: 07 May 2009 09:27
Last Modified: 07 Jan 2016 16:25

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